SRLIW

Shift Right Logical Immediate Word

SRLIW rd, rs1, shamt

Logically shifts the lower 32 bits of rs1 right by a constant, sign-extending the result.

Encoding

Binary Layout

0000000

31:25

shamtw

24:20

rs1

19:15

101

14:12

rd

11:7

0011011

6:0

 

Format I-Type (Shift)

Opcode 0x0000501B

Extension RV64I

Operands

• rd
  Destination register (integer)
• rs1
  Source
• shamt
  Shift Amount

Example

SRLIW x10, x11, 4

// Logical right shift of lower word.

Related

More in RV64I

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

SRLIW performs a logical right shift of the lower 32 bits of rs1 by the 5-bit immediate, sign-extends the 32-bit result to 64 bits, and writes it to rd.

Operation

R[rd] = sext((R[rs1][31:0] >>u shamt));