VMULHU.VV

Vector Multiply High Unsigned

VMULHU.VV vd, vs2, vs1, vm

Multiplies unsigned integers and keeps the high N bits.

Details

Performs element-wise high-half multiply unsigned on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.

Pseudocode Operation

foreach(i < vl): vd[i] = (zext(vs1[i]) * zext(vs2[i])) >> SEW;

Example

VMULHU.VV v1, v4, v2, v0.t

Encoding

Binary Layout
100100
31:26
vm
25
vs2
24:20
vs1
19:15
000
14:12
vd
11:7
1010111
6:0
 
Format OPIVV
Opcode 0x57
Extension V

Operands

  • vd
    Destination vector register
  • vs2
    Source vector register 2
  • vs1
    Source vector register 1