VMIN.VV

Vector Minimum (Signed)

VMIN.VV vd, vs2, vs1, vm

Computes the signed minimum of elements in two vectors.

Encoding

Binary Layout

000101

31:26

vm

25

vs2

24:20

vs1

19:15

000

14:12

vd

11:7

1010111

6:0

 

Format OPIVV

Opcode 0x14000057

Extension V

Operands

• vd
  Destination vector register
• vs2
  Source vector register 2
• vs1
  Source vector register 1

Example

VMIN.VV v1, v4, v2, v0.t

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs element-wise signed minimum on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.

Operation

foreach(i < vl): vd[i] = min(vs1[i], vs2[i]);