VMSLEU.VV

Vector Mask Set Less or Equal (Unsigned)

VMSLEU.VV vd, vs2, vs1, vm

Sets mask if vs2 <= vs1 (Unsigned).

Encoding

Binary Layout

011100

31:26

vm

25

vs2

24:20

vs1

19:15

000

14:12

vd

11:7

1010111

6:0

 

Format OPIVV

Opcode 0x70000057

Extension V

Operands

• vd
  Mask
• vs2
  Source vector register 2
• vs1
  Source vector register 1

Example

VMSLEU.VV v1, v4, v2, v0.t

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Compares elements element-wise for less than or equal and writes a mask result to vd.

Operation

vd = (vs2 <=u vs1);