V Instructions

171 RISC-V instructions in this extension - showing 100 per page, page 1 of 2 - click any row for encoding, pseudocode, and full documentation.

Mnemonic ⇅ Syntax Format ⇅ Summary
VAADD.VV VAADD.VV vd, vs2, vs1, vm OPIVV Computes (vs1 + vs2) >> 1 with rounding.
VAADDU.VV VAADDU.VV vd, vs2, vs1, vm OPIVV Computes (a + b + 1) >> 1 for unsigned integers.
VADC.VVM VADC.VVM vd, vs2, vs1, v0 OPIVV Computes vd = vs1 + vs2 + carry (v0).
VADD.VI VADD.VI vd, vs2, imm, vm OPIVI Adds immediate to vector.
VADD.VV VADD.VV vd, vs2, vs1, vm OPIVV Adds elements of two vector registers.
VAND.VI VAND.VI vd, vs2, imm, vm OPIVI Bitwise AND with immediate.
VASUB.VV VASUB.VV vd, vs2, vs1, vm OPIVV Computes (a - b) >> 1 for signed integers.
VASUBU.VV VASUBU.VV vd, vs2, vs1, vm OPIVV Computes (a - b) >> 1 for unsigned integers.
VCOMPRESS.VM VCOMPRESS.VM vd, vs2, vs1 OPMVV Compacts elements from source vector into contiguous elements in dest where the mask is 1.
VCPOP.M VCPOP.M rd, vs2, vm OPMVX Counts set bits in the source mask register.
VDIV.VV VDIV.VV vd, vs2, vs1, vm OPIVV Divides signed vector elements.
VDIVU.VV VDIVU.VV vd, vs2, vs1, vm OPIVV Divides unsigned vector elements.
VFADD.VV VFADD.VV vd, vs2, vs1, vm OPFVV Adds elements of two vector registers (Floating Point).
VFCLASS.V VFCLASS.V vd, vs2, vm OPFVV Classifies elements of a float vector (NaN, Inf, etc.).
VFCVT.F.X.V VFCVT.F.X.V vd, vs2, vm OPFVV Converts signed integer elements to floating-point.
VFCVT.X.F.V VFCVT.X.F.V vd, vs2, vm OPFVV Converts floating-point elements to signed integers.
VFDIV.VV VFDIV.VV vd, vs2, vs1, vm OPFVV Divides elements of two floating-point vectors.
VFIRST.M VFIRST.M rd, vs2, vm OPMVX Finds the index of the first set bit in the mask.
VFMADD.VV VFMADD.VV vd, vs1, vs2, vm OPFVV Computes (vs1 * vs2) + vd (overwriting vd) with single rounding.
VFMAX.VV VFMAX.VV vd, vs2, vs1, vm OPFVV Writes the larger of two floating-point vector elements to vd.
VFMIN.VV VFMIN.VV vd, vs2, vs1, vm OPFVV Writes the smaller of two floating-point vector elements to vd.
VFMUL.VV VFMUL.VV vd, vs2, vs1, vm OPFVV Multiplies elements of two floating-point vectors.
VFMV.F.S VFMV.F.S fd, vs2 OPFVW Moves element 0 of a float vector to a scalar float register.
VFMV.S.F VFMV.S.F vd, fs1 OPFVW Moves a scalar float register to element 0 of a vector.
VFNCVT.F.F.W VFNCVT.F.F.W vd, vs2, vm OPFVV Converts 2*N-bit floats to N-bit floats (e.g., FP32 -> FP16).
VFNCVT.X.F.W VFNCVT.X.F.W vd, vs2, vm OPFVV Converts 2*N-bit float to N-bit signed integer.
VFREC7.V VFREC7.V vd, vs2, vm OPFVV Computes an estimate of 1/x (7-bit precision). Used for fast division/normalization loops.
VFREDMAX.VS VFREDMAX.VS vd, vs2, vs1, vm OPFVV Reduces a float vector to a scalar by finding the maximum element.
VFREDOSUM.VS VFREDOSUM.VS vd, vs2, vs1, vm OPFVV Sums float vector elements in exact order (0 to vl-1).
VFREDUSUM.VS VFREDUSUM.VS vd, vs2, vs1, vm OPFVV Reduces a float vector to a scalar by summing elements (Order not preserved, faster).
VFRSQRT7.V VFRSQRT7.V vd, vs2, vm OPFVV Computes an estimate of 1/sqrt(x). Critical for vector normalization.
VFSGNJ.VV VFSGNJ.VV vd, vs2, vs1, vm OPFVV Injects the sign of vs2 into vs1 (Copy Sign).
VFSQRT.V VFSQRT.V vd, vs2, vm OPFVV Computes the square root of elements in a floating-point vector.
VFWADD.VV VFWADD.VV vd, vs2, vs1, vm OPFVV Adds N-bit floats to produce 2*N-bit float results (e.g., FP16 + FP16 -> FP32).
VFWCVT.F.F.V VFWCVT.F.F.V vd, vs2, vm OPFVV Converts N-bit floats to 2*N-bit floats (e.g., FP16 -> FP32).
VFWCVT.F.X.V VFWCVT.F.X.V vd, vs2, vm OPFVV Converts N-bit integers to 2*N-bit floats (e.g., Int16 -> FP32).
VFWCVT.X.F.V VFWCVT.X.F.V vd, vs2, vm OPFVV Converts N-bit float to 2*N-bit signed integer.
VFWMUL.VV VFWMUL.VV vd, vs2, vs1, vm OPFVV Multiplies N-bit floats to produce 2*N-bit float results.
VFWREDOSUM.VS VFWREDOSUM.VS vd, vs2, vs1, vm OPFVV Sums N-bit floats into 2*N-bit scalar accumulator (Ordered).
VFWREDUSUM.VS VFWREDUSUM.VS vd, vs2, vs1, vm OPFVV Sums N-bit floats into 2*N-bit scalar accumulator (Unordered).
VID.V VID.V vd, vm OPMVV Writes the element index (0, 1, 2...) to the destination.
VIOTA.M VIOTA.M vd, vs2, vm OPMVV Writes the index of the active element to the destination. Useful for parallel prefix sums.
VLE16.V VLE16.V vd, (rs1), vm VL-Type Loads a vector of 16-bit elements from memory.
VLE16FF.V VLE16FF.V vd, (rs1), vm VL-Type Loads 16-bit elements with fault suppression.
VLE32.V VLE32.V vd, (rs1), vm V-Load Loads a vector of 32-bit elements from memory into a vector register.
VLE32FF.V VLE32FF.V vd, (rs1), vm VL-Type Loads 32-bit elements with fault suppression.
VLE64.V VLE64.V vd, (rs1), vm VL-Type Loads a vector of 64-bit elements from memory.
VLE64FF.V VLE64FF.V vd, (rs1), vm VL-Type Loads 64-bit elements with fault suppression.
VLE8.V VLE8.V vd, (rs1), vm VL-Type Loads a vector of 8-bit elements from memory.
VLE8FF.V VLE8FF.V vd, (rs1), vm VL-Type Loads 8-bit elements, suppressing faults on elements after the first. Sets VL to number of elements loaded. Critical for strings.
VLM.V VLM.V vd, (rs1) VL-Type Loads a vector mask register from memory.
VLOXEI32.V VLOXEI32.V vd, (rs1), vs2, vm VL-Type Loads elements using indices, ensuring order (useful for I/O buffers).
VLSE32.V VLSE32.V vd, (rs1), rs2, vm VL-Type Loads elements from memory with a fixed stride.
VLSEG2E16.V VLSEG2E16.V vd, (rs1), vm VL-Type Loads 2 fields (e.g., Complex Real/Imag) of 16-bit elements.
VLSEG3E8.V VLSEG3E8.V vd, (rs1), vm VL-Type Loads 3 fields (e.g., RGB) of 8-bit elements into 3 vector registers.
VLSEG4E8.V VLSEG4E8.V vd, (rs1), vm VL-Type Loads 4 fields (e.g., RGBA) of 8-bit elements into 4 vector registers.
VLUXEI32.V VLUXEI32.V vd, (rs1), vs2, vm VL-Type Loads elements from memory using a vector of indices (Gather).
VMACC.VV VMACC.VV vd, vs1, vs2, vm OPIVV Computes vd = vd + (vs1 * vs2). Essential for dot products.
VMADC.VIM VMADC.VIM vd, vs2, imm, v0 OPIVI Add Immediate with Carry.
VMADC.VVM VMADC.VVM vd, vs2, vs1, v0 OPIVV Adds two vectors and a carry-in, producing the carry-out to the destination mask.
VMAND.MM VMAND.MM vd, vs2, vs1 OPMVV Performs bitwise AND on vector mask registers.
VMANDN.MM VMANDN.MM vd, vs2, vs1 OPMVV Computes vd = vs1 & ~vs2 (mask operation).
VMAX.VV VMAX.VV vd, vs2, vs1, vm OPIVV Computes the signed maximum of elements in two vectors.
VMAXU.VV VMAXU.VV vd, vs2, vs1, vm OPIVV Computes the unsigned maximum of elements in two vectors.
VMERGE.VIM VMERGE.VIM vd, vs2, imm, v0 OPIVI Merges immediate vs vector based on mask.
VMERGE.VVM VMERGE.VVM vd, vs2, vs1, v0 OPIVV Merges two vectors based on the mask (if mask=0, pick vs2; if mask=1, pick vs1).
VMERGE.VXM VMERGE.VXM vd, vs2, rs1, v0 OPIVX Merges integer scalar vs vector based on mask.
VMFEQ.VV VMFEQ.VV vd, vs2, vs1, vm OPFVV Compares float vectors for equality, writing result to mask register.
VMFLE.VV VMFLE.VV vd, vs2, vs1, vm OPFVV Compares float vectors (vs2 <= vs1), writing result to mask register.
VMFLT.VV VMFLT.VV vd, vs2, vs1, vm OPFVV Compares float vectors (vs2 < vs1), writing result to mask register.
VMIN.VV VMIN.VV vd, vs2, vs1, vm OPIVV Computes the signed minimum of elements in two vectors.
VMINU.VV VMINU.VV vd, vs2, vs1, vm OPIVV Computes the unsigned minimum of elements in two vectors.
VMNAND.MM VMNAND.MM vd, vs2, vs1 OPMVV Performs bitwise NAND on vector mask registers. Used to invert masks (NOT).
VMORN.MM VMORN.MM vd, vs2, vs1 OPMVV Computes vd = vs1 | ~vs2 (mask operation).
VMSBC.VV VMSBC.VV vd, vs2, vs1 OPMVV Writes a mask where bits are 1 before the first element in vs2 that is 1.
VMSBF.M VMSBF.M vd, vs2, vm OPMVV Sets mask bits before the first set bit in the source mask.
VMSEQ.VI VMSEQ.VI vd, vs2, imm, vm OPIVI Sets mask if element == imm.
VMSEQ.VV VMSEQ.VV vd, vs2, vs1, vm OPIVV Sets destination mask bit if elements are equal.
VMSGE.VV VMSGE.VV vd, vs2, vs1, vm OPIVV Sets mask if vs2 >= vs1.
VMSGEU.VV VMSGEU.VV vd, vs2, vs1, vm OPIVV Sets mask if vs2 >= vs1 (Unsigned).
VMSGT.VV VMSGT.VV vd, vs2, vs1, vm OPIVV Sets mask if vs2 > vs1.
VMSGTU.VV VMSGTU.VV vd, vs2, vs1, vm OPIVV Sets mask if vs2 > vs1 (Unsigned).
VMSIF.M VMSIF.M vd, vs2, vm OPMVV Sets mask bits up to and including the first set bit in the source.
VMSLE.VI VMSLE.VI vd, vs2, imm, vm OPIVI Sets mask if element <= imm (Signed).
VMSLE.VV VMSLE.VV vd, vs2, vs1, vm OPIVV Sets mask if vs2 <= vs1.
VMSLEU.VI VMSLEU.VI vd, vs2, imm, vm OPIVI Sets mask if element <= imm (Unsigned).
VMSLEU.VV VMSLEU.VV vd, vs2, vs1, vm OPIVV Sets mask if vs2 <= vs1 (Unsigned).
VMSLT.VI VMSLT.VI vd, vs2, imm, vm OPIVI Sets mask if element < imm (Signed).
VMSLT.VV VMSLT.VV vd, vs2, vs1, vm OPIVV Sets destination mask bit if vs2 < vs1 (signed).
VMSLTU.VI VMSLTU.VI vd, vs2, imm, vm OPIVI Sets mask if element < imm (Unsigned).
VMSLTU.VV VMSLTU.VV vd, vs2, vs1, vm OPIVV Sets destination mask bit if vs2 < vs1 (unsigned).
VMSNE.VI VMSNE.VI vd, vs2, imm, vm OPIVI Sets mask if element != imm.
VMSOF.M VMSOF.M vd, vs2, vm OPMVV Sets only the first set bit from the source mask.
VMUL.VV VMUL.VV vd, vs2, vs1, vm OPIVV Multiplies elements of two vector registers.
VMULH.VV VMULH.VV vd, vs2, vs1, vm OPIVV Multiplies signed integers and keeps the high N bits.
VMULHU.VV VMULHU.VV vd, vs2, vs1, vm OPIVV Multiplies unsigned integers and keeps the high N bits.
VMV.S.X VMV.S.X vd, rs1 OPMVX Copies an integer register to element 0 of a vector.
VMV.V.V VMV.V.V vd, vs1 OPIVV Copies a vector register.
VMV.X.S VMV.X.S rd, vs2 OPMVX Copies element 0 of a vector to an integer register.
VMV1R.V VMV1R.V vd, vs2 OPVI Moves a single vector register to another, ignoring VL and VTYPE (used for spilling).