VLSEG2E16.V

Vector Load Segment (2 fields, 16-bit)

VLSEG2E16.V vd, (rs1), vm

Loads 2 fields (e.g., Complex Real/Imag) of 16-bit elements.

Details

Performs a vector strided load of 2-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.

Pseudocode Operation

Load 2 interleaved 16-bit streams.

Example

VLSEG2E16.V v1, a0, v0.t

Encoding

Binary Layout
000110
31:26
00011
25:21
vm
20
rs1
19:15
101
14:12
vd
11:7
0000111
6:0
 
Format VL-Type
Opcode 0x07
Extension V

Operands

  • vd
    Dest Group (2 regs)
  • rs1
    Base Addr