FADD.H

Float Add Half

FADD.H rd, rs1, rs2

Performs 16-bit floating-point addition.

Details

Performs half-precision (16-bit) floating-point addition. The operation adds the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.

Pseudocode Operation

F[rd] = F[rs1] + F[rs2];

Example

FADD.H f0, f1, f2

Encoding

Binary Layout
0000100
31:25
rs2
24:20
rs1
19:15
000
14:12
rd
11:7
1010011
6:0
 
Format R-Type
Opcode 0x53
Extension Zfh

Operands

  • rd
    Destination register (integer)
  • rs1
    Source register 1 (integer)
  • rs2
    Source register 2 (integer)