VSMUL.VV

Vector Single-Width Saturating Multiply

VSMUL.VV vd, vs2, vs1, vm

Performs signed saturating multiplication, keeping the high half of the product (Fixed-point support).

Details

Performs a vector mask register store of element-sized-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.

Pseudocode Operation

foreach(i < vl): vd[i] = (sext(vs1[i]) * sext(vs2[i])) >> (SEW-1);

Example

VSMUL.VV v1, v4, v2, v0.t

Encoding

Binary Layout
111101
31:26
vm
25
vs2
24:20
vs1
19:15
000
14:12
vd
11:7
1010111
6:0
 
Format OPIVV
Opcode 0x57
Extension V

Operands

  • vd
    Destination vector register
  • vs2
    Source vector register 2
  • vs1
    Source vector register 1