VWMACCUS.VX

Vector Widening MAC (Unsigned * Signed)

VWMACCUS.VX vd, rs1, vs2, vm

vd = vd + (unsigned(vs1) * signed(vs2)).

Encoding

Binary Layout

111110

31:26

vm

25

vs2

24:20

vs1

19:15

000

14:12

vd

11:7

1010111

6:0

 

Format OPIVV

Opcode 0xF8006057

Extension V

Operands

• vd
  Acc
• vs1
  Unsigned
• vs2
  Signed

Example

VWMACCUS.VX v1, x10, v2, v0.t

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.

Operation

vd += zext(vs1) * sext(vs2);