VSRA.VI

Vector Shift Right Arithmetic Immediate

VSRA.VI vd, vs2, imm, vm

Shifts elements right (arithmetic) by immediate.

Encoding

Binary Layout

101001

31:26

vm

25

vs2

24:20

zimm5

19:15

011

14:12

vd

11:7

1010111

6:0

 

Format OPIVI

Opcode 0xA4003057

Extension V

Operands

• vd
  Destination vector register
• vs2
  Source vector register 2
• imm
  Signed immediate value

Example

VSRA.VI v1, v4, 16, v0.t

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs element-wise right arithmetic shift on a vector and an immediate, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.

Operation

vd = vs2 >>s imm;