ANDN

AND Not

ANDN rd, rs1, rs2

Performs bitwise AND with the bitwise negation of rs2 (rs1 & ~rs2).

Encoding

Binary Layout

0100000

31:25

rs2

24:20

rs1

19:15

111

14:12

rd

11:7

0110011

6:0

 

Format R-Type

Opcode 0x40007033

Extension Zbb

Operands

• rd
  Destination register (integer)
• rs1
  Source register 1 (integer)
• rs2
  Source 2 (Inverted)

Example

ANDN x10, x11, x12

// Clear bits in x11 that are set in x12.

Related

More in Zbb

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

ANDN computes the bitwise AND of rs1 with the bitwise NOT of rs2, writing the result to rd. Equivalent to rd = rs1 & ~rs2.

Operation

R[rd] = R[rs1] & ~R[rs2];