ADDI

Add Immediate

ADDI rd, rs1, imm

Adds a register and a sign-extended 12-bit immediate value.

Encoding

Binary Layout

imm12

31:20

rs1

19:15

000

14:12

rd

11:7

0010011

6:0

 

Format I-Type

Opcode 0x00000013

Extension RV32I

Operands

• rd
  Destination Register
• rs1
  Source Register
• imm
  12-bit Signed Immediate

Example

ADDI x5, x6, 10

// Adds 10 to the value in x6 and stores it in x5.

Related

Across architectures

Integer Addition : how x86, ARM, RISC-V, and PowerISA each do this.

More in RV32I

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

ADDI adds the sign-extended 12-bit immediate to register rs1 and writes the low XLEN bits to rd. Arithmetic overflow is ignored. ADDI rd, rs1, 0 implements the MV assembler pseudoinstruction.

Operation

R[rd] = R[rs1] + sext(imm);