ADDI

Add Immediate

ADDI rd, rs1, imm

Adds a register and a sign-extended 12-bit immediate value.

Details

ADDI adds the sign-extended 12-bit immediate to register rs1 and writes the low XLEN bits to rd. Arithmetic overflow is ignored. ADDI rd, rs1, 0 implements the MV assembler pseudoinstruction.

Pseudocode Operation

R[rd] = R[rs1] + sext(imm);

Example

ADDI x5, x6, 10

Encoding

Binary Layout
imm[11:0]
31:20
rs1
19:15
000
14:12
rd
11:7
0010011
6:0
 
Format I-Type
Opcode 0x13
Extension RV32I

Operands

  • rd
    Destination Register
  • rs1
    Source Register
  • imm
    12-bit Signed Immediate