VWMACCSU.VV

Vector Widening MAC (Signed * Unsigned)

VWMACCSU.VV vd, vs1, vs2, vm

vd = vd + (signed(vs1) * unsigned(vs2)).

Encoding

Binary Layout

111111

31:26

vm

25

vs2

24:20

vs1

19:15

010

14:12

vd

11:7

1010111

6:0

 

Format OPIVV

Opcode 0xFC002057

Extension V

Operands

• vd
  Acc
• vs1
  Signed
• vs2
  Unsigned

Example

VWMACCSU.VV v1, v2, v4, v0.t

Related

More in V

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs a widening operation, producing results twice as wide as the source elements. Results are written to vd using 2× the element grouping (EEW). The number of elements and masking are governed by vl and vm.

Operation

vd += sext(vs1) * zext(vs2);