VSSEG2E16.V

Vector Store Segment (2 fields, 16-bit)

VSSEG2E16.V vs3, (rs1), vm

Stores 2 vector registers as interleaved 16-bit fields.

Details

Performs a vector strided store of 2-bit elements from/to memory. The number of elements transferred is determined by vl. Masking is controlled by vm.

Pseudocode Operation

Store 2 interleaved 16-bit streams.

Example

VSSEG2E16.V v6, a0, v0.t

Encoding

Binary Layout
000110
31:26
00011
25:21
vm
20
rs1
19:15
101
14:12
vs3
11:7
0100111
6:0
 
Format VS-Type
Opcode 0x27
Extension V

Operands

  • vs3
    Src Group (2 regs)
  • rs1
    Base Addr