FENCE.I
Instruction Fence
FENCE.I
Synchronizes the instruction cache with the data cache (used after self-modifying code).
Encoding
Binary Layout
imm12
31:20
rs1
19:15
001
14:12
rd
11:7
0001111
6:0
Operands
Related
Across architectures
Instruction Cache Synchronisation : how x86, ARM, RISC-V, and PowerISA each do this.
More in Zifencei
Reference
View in RISC-V Unprivileged ISA Specification ↗
RISC-V ISA Manual
Description
FENCE.I synchronises the instruction and data streams. It ensures that any stores to instruction memory visible to the current hart are made visible to subsequent instruction fetches by that hart.
Operation
Fence(Store, Fetch);