FEQ.S

Float Equal (Single)

FEQ.S rd, rs1, rs2

Sets integer rd to 1 if float rs1 equals float rs2, else 0.

Encoding

Binary Layout

1010000

31:25

rs2

24:20

rs1

19:15

010

14:12

rd

11:7

1010011

6:0

 

Format R-Type

Opcode 0xA0002053

Extension F

Operands

• rd
  Dest (Integer)
• rs1
  Src 1 (Float)
• rs2
  Src 2 (Float)

Example

FEQ.S x10, f1, f2

// x10 = (f1 == f2)

Related

More in F

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs a single-precision (32-bit) floating-point equality comparison and writes 1 (true) or 0 (false) to integer rd. NaN inputs produce 0 (unordered), except FEQ which raises invalid-operation if either operand is a signalling NaN.

Operation

R[rd] = (F[rs1] == F[rs2]) ? 1 : 0;