FMADD.S

Float Fused Multiply-Add (Single)

FMADD.S rd, rs1, rs2, rs3

Computes (rs1 * rs2) + rs3 with a single rounding.

Encoding

Binary Layout

rs3

31:27

00

26:25

rs2

24:20

rs1

19:15

rm

14:12

rd

11:7

1000011

6:0

 

Format R4-Type

Opcode 0x00000043

Extension F

Operands

• rd
  Destination register (integer)
• rs1
  Source register 1 (integer)
• rs2
  Source register 2 (integer)
• rs3
  Src 3

Example

FMADD.S f0, f1, f2, f3

// f0 = (f1 * f2) + f3

Related

Across architectures

Fused Multiply-Add : how x86, ARM, RISC-V, and PowerISA each do this.

More in F

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs single-precision (32-bit) floating-point fused multiply-add. The operation computes fused multiply-add on the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.

Operation

F[rd] = (F[rs1] * F[rs2]) + F[rs3];