MULHSU

Multiply High Signed-Unsigned

MULHSU rd, rs1, rs2

Multiplies signed rs1 by unsigned rs2 and returns the upper XLEN bits.

Encoding

Binary Layout

0000001

31:25

rs2

24:20

rs1

19:15

010

14:12

rd

11:7

0110011

6:0

 

Format R-Type

Opcode 0x02002033

Extension M

Operands

• rd
  Dest (Upper Bits)
• rs1
  Signed Source
• rs2
  Unsigned Source

Example

MULHSU t0, a0, a1

Related

More in M

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

MULHSU multiplies rs1 (signed) by rs2 (unsigned) and writes the upper XLEN bits of the product to rd.

Operation

R[rd] = (sext(R[rs1]) * zext(R[rs2])) >> XLEN;