MUL

Multiply

MUL rd, rs1, rs2

Performs a 32-bit (or 64-bit) multiplication of rs1 and rs2 and stores the lower bits in rd.

Encoding

Binary Layout

0000001

31:25

rs2

24:20

rs1

19:15

000

14:12

rd

11:7

0110011

6:0

 

Format R-Type

Opcode 0x02000033

Extension M

Operands

• rd
  Dest (Lower Bits)
• rs1
  Source register 1 (integer)
• rs2
  Source register 2 (integer)

Example

MUL x10, x11, x12

// x10 = lower bits of x11 * x12.

Related

Across architectures

Integer Multiply : how x86, ARM, RISC-V, and PowerISA each do this.

More in M

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

MUL performs an XLEN-bit × XLEN-bit multiplication of rs1 and rs2 and writes the lower XLEN bits of the product to rd. Both operands are treated as signed or unsigned (the result is the same for the low bits).

Operation

R[rd] = (R[rs1] * R[rs2])[XLEN-1:0];