M Instructions
13 RISC-V instructions in this extension - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| DIV | DIV rd, rs1, rs2 | R-Type | Performs signed integer division. |
| DIVU | DIVU rd, rs1, rs2 | R-Type | Performs unsigned integer division. |
| DIVUW | DIVUW rd, rs1, rs2 | R-Type | Performs 32-bit unsigned division of rs1 by rs2, sign-extending the result. |
| DIVW | DIVW rd, rs1, rs2 | R-Type | Performs 32-bit signed division of rs1 by rs2, sign-extending the result. |
| MUL | MUL rd, rs1, rs2 | R-Type | Performs a 32-bit (or 64-bit) multiplication of rs1 and rs2 and stores the lower bits in rd. |
| MULH | MULH rd, rs1, rs2 | R-Type | Performs a signed multiplication and stores the upper bits of the result. |
| MULHSU | MULHSU rd, rs1, rs2 | R-Type | Multiplies signed rs1 by unsigned rs2 and returns the upper XLEN bits. |
| MULHU | MULHU rd, rs1, rs2 | R-Type | Performs unsigned multiplication and returns the upper XLEN bits. |
| MULW | MULW rd, rs1, rs2 | R-Type | Performs 32-bit multiplication of rs1 and rs2, sign-extending the 32-bit result to 64 bits. |
| REM | REM rd, rs1, rs2 | R-Type | Computes the signed remainder of division. |
| REMU | REMU rd, rs1, rs2 | R-Type | Computes the unsigned remainder of division. |
| REMUW | REMUW rd, rs1, rs2 | R-Type | Computes the remainder of 32-bit unsigned division, sign-extending the result. |
| REMW | REMW rd, rs1, rs2 | R-Type | Computes the remainder of 32-bit signed division, sign-extending the result. |