MULW

Multiply Word

MULW rd, rs1, rs2

Performs 32-bit multiplication of rs1 and rs2, sign-extending the 32-bit result to 64 bits.

Details

MULW multiplies the lower 32 bits of rs1 and rs2, sign-extends the lower 32 bits of the product to 64 bits, and writes to rd (RV64 only).

Pseudocode Operation

R[rd] = sext((R[rs1] * R[rs2])[31:0]);

Example

MULW x10, x11, x12

Encoding

Binary Layout
0000001
31:25
rs2
24:20
rs1
19:15
000
14:12
rd
11:7
0111011
6:0
 
Format R-Type
Opcode 0x3B
Extension M

Operands

  • rd
    Destination register (integer)
  • rs1
    Source register 1 (integer)
  • rs2
    Source register 2 (integer)