FLD

Float Load Double

FLD rd, offset(rs1)

Loads a 64-bit double-precision floating-point value from memory.

Encoding

Binary Layout

imm12

31:20

rs1

19:15

011

14:12

rd

11:7

0000111

6:0

 

Format I-Type

Opcode 0x00003007

Extension D

Operands

• rd
  Dest (Float Reg)
• rs1
  Base Address
• offset
  Offset

Example

FLD f1, 8(x10)

// Loads double from address x10+8.

Related

More in D

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Loads a 64-bit doubleword from memory at address rs1+sext(offset) into floating-point register rd.

Operation

F[rd] = M[R[rs1] + sext(offset)][63:0];