D Instructions
32 RISC-V instructions in this extension - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| FADD.D | FADD.D rd, rs1, rs2 | R-Type | Performs double-precision floating-point addition. |
| FCLASS.D | FCLASS.D rd, rs1 | R-Type | Examines a double-precision register and generates a classification bitmask. |
| FCVT.D.L | FCVT.D.L rd, rs1 | I-Type (Float) | Converts a 64-bit signed integer to a double-precision float. |
| FCVT.D.LU | FCVT.D.LU rd, rs1 | I-Type (Float) | Converts a 64-bit unsigned integer to a double-precision float. |
| FCVT.D.S | FCVT.D.S rd, rs1 | I-Type (Float) | Converts a single-precision float to a double-precision float. |
| FCVT.D.W | FCVT.D.W rd, rs1 | I-Type (Float) | Converts a 32-bit signed integer to a double-precision float. |
| FCVT.D.WU | FCVT.D.WU rd, rs1 | I-Type (Float) | Converts a 32-bit unsigned integer to a double-precision float. |
| FCVT.L.D | FCVT.L.D rd, rs1 | I-Type (Float) | Converts a double-precision float to a 64-bit signed integer. |
| FCVT.LU.D | FCVT.LU.D rd, rs1 | I-Type (Float) | Converts a double-precision float to a 64-bit unsigned integer. |
| FCVT.S.D | FCVT.S.D rd, rs1 | I-Type (Float) | Converts a double-precision float to a single-precision float. |
| FCVT.W.D | FCVT.W.D rd, rs1 | I-Type (Float) | Converts a double-precision float to a 32-bit signed integer. |
| FCVT.WU.D | FCVT.WU.D rd, rs1 | I-Type (Float) | Converts a double-precision float to a 32-bit unsigned integer. |
| FDIV.D | FDIV.D rd, rs1, rs2 | R-Type | Performs double-precision floating-point division. |
| FEQ.D | FEQ.D rd, rs1, rs2 | R-Type | Sets integer rd to 1 if double rs1 equals double rs2, else 0. |
| FLD | FLD rd, offset(rs1) | I-Type | Loads a 64-bit double-precision floating-point value from memory. |
| FLE.D | FLE.D rd, rs1, rs2 | R-Type | Sets integer rd to 1 if double rs1 is less than or equal to double rs2, else 0. |
| FLT.D | FLT.D rd, rs1, rs2 | R-Type | Sets integer rd to 1 if double rs1 is less than double rs2, else 0. |
| FMADD.D | FMADD.D rd, rs1, rs2, rs3 | R4-Type | Computes (rs1 * rs2) + rs3 with a single rounding (64-bit). |
| FMAX.D | FMAX.D rd, rs1, rs2 | R-Type | Writes the larger of two double-precision floating-point values to rd. |
| FMIN.D | FMIN.D rd, rs1, rs2 | R-Type | Writes the smaller of two double-precision floating-point values to rd. |
| FMSUB.D | FMSUB.D rd, rs1, rs2, rs3 | R4-Type | Computes (rs1 * rs2) - rs3 with a single rounding (Double). |
| FMUL.D | FMUL.D rd, rs1, rs2 | R-Type | Performs double-precision floating-point multiplication. |
| FMV.D.X | FMV.D.X rd, rs1 | I-Type (Float) | Moves the bit pattern of a 64-bit integer register to a floating-point register (RV64). |
| FMV.X.D | FMV.X.D rd, rs1 | I-Type (Float) | Moves the bit pattern of a 64-bit floating-point register to an integer register (RV64). |
| FNMADD.D | FNMADD.D rd, rs1, rs2, rs3 | R4-Type | Computes -(rs1 * rs2) - rs3 with a single rounding (Double). |
| FNMSUB.D | FNMSUB.D rd, rs1, rs2, rs3 | R4-Type | Computes -(rs1 * rs2) + rs3 with a single rounding (Double). |
| FSD | FSD rs2, offset(rs1) | S-Type | Stores a 64-bit double-precision floating-point value to memory. |
| FSGNJ.D | FSGNJ.D rd, rs1, rs2 | R-Type | Injects the sign of rs2 into rs1 (Double Precision). |
| FSGNJN.D | FSGNJN.D rd, rs1, rs2 | R-Type | Injects the *negated* sign of rs2 into rs1 (Double Precision). |
| FSGNJX.D | FSGNJX.D rd, rs1, rs2 | R-Type | Injects the XOR of signs of rs1 and rs2 (Double Precision). |
| FSQRT.D | FSQRT.D rd, rs1 | I-Type (Float) | Computes the square root of a double-precision floating-point number. |
| FSUB.D | FSUB.D rd, rs1, rs2 | R-Type | Performs double-precision floating-point subtraction. |