FDIV.H

Float Divide (Half)

FDIV.H rd, rs1, rs2

Performs 16-bit floating-point division.

Details

Performs half-precision (16-bit) floating-point division. The operation divides the source operand(s), rounds the result according to the dynamic rounding mode in fcsr, and writes to fd. NaN and infinity propagation follow IEEE 754-2008.

Pseudocode Operation

F[rd] = F[rs1] / F[rs2];

Example

FDIV.H t0, a0, a1

Encoding

Binary Layout
0001100
31:25
rs2
24:20
rs1
19:15
rm
rd
14:10
1010011
9:3
 
Format R-Type
Opcode 0x53
Extension Zfh

Operands

  • rd
    Destination register (integer)
  • rs1
    Dividend
  • rs2
    Divisor