VAESKF1.VI

Vector AES Key Expansion 1

VAESKF1.VI vd, vs2, uimm

Generates the next round key for AES (Step 1).

Encoding

Binary Layout

1000101

31:25

vs2

24:20

zimm5

19:15

010

14:12

vd

11:7

1110111

6:0

 

Format OPIVI

Opcode 0x8A002077

Extension Zvkned

Operands

• vd
  Destination vector register
• vs2
  Source vector register 2
• uimm
  RCON

Example

VAESKF1.VI v1, v4, 4

Related

More in Zvkned

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

Performs a vectorised AES cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.

Operation

vd = AES_KeyGen_1(vs2, uimm);