VAESKF1.VI

Vector AES Key Expansion 1

VAESKF1.VI vd, vs2, uimm

Generates the next round key for AES (Step 1).

Details

Performs a vectorised AES cryptographic round operation. Each element group undergoes one step of the cipher algorithm in parallel. See the Zvk vector crypto extension for full semantic details.

Pseudocode Operation

vd = AES_KeyGen_1(vs2, uimm);

Example

VAESKF1.VI v1, v4, 4

Encoding

Binary Layout
100010
31:26
1
25
vs2
24:20
uimm
010
19:17
vd
16:12
1010111
11:5
 
Format OPIVI
Opcode 0x57
Extension Zvkned

Operands

  • vd
    Destination vector register
  • vs2
    Source vector register 2
  • uimm
    RCON