LR.W

Load Reserved Word

LR.W rd, (rs1)

Loads a word from memory and registers a reservation set for the address.

Encoding

Binary Layout

00010

31:27

aq

26

rl

25

00000

24:20

rs1

19:15

010

14:12

rd

11:7

0101111

6:0

 

Format R-Type (Atomic)

Opcode 0x1000202F

Extension A

Operands

• rd
  Destination Register
• rs1
  Address

Example

LR.W x10, (x11)

// Start atomic read-modify-write sequence.

Related

Across architectures

Atomic Compare and Swap : how x86, ARM, RISC-V, and PowerISA each do this.

More in A

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

LR.W loads a word from the memory address in rs1 into rd and registers a reservation on that address. The reservation is used by SC.W to implement load-reserved/store-conditional atomics.

Operation

R[rd] = LoadReserved32(M[R[rs1]]);