LR.D

Load Reserved Doubleword

LR.D rd, (rs1)

Loads a doubleword from memory and registers a reservation set.

Encoding

Binary Layout

00010

31:27

aq

26

rl

25

00000

24:20

rs1

19:15

011

14:12

rd

11:7

0101111

6:0

 

Format R-Type (Atomic)

Opcode 0x1000302F

Extension A

Operands

• rd
  Destination Register
• rs1
  Address

Example

LR.D x10, (x11)

// 64-bit atomic load reserved.

Related

Across architectures

Load-Acquire : how x86, ARM, RISC-V, and PowerISA each do this.

More in A

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

LR.D loads a doubleword from the memory address in rs1 into rd and registers a reservation on that address (RV64 only).

Operation

R[rd] = LoadReserved64(M[R[rs1]]);