Load-Acquire
A load that prevents later memory accesses from being reordered before it.
Memory Ordering
Semantics
Acquire semantics: no memory operation after the load may become visible before it. On x86 an ordinary load already carries acquire semantics under TSO, so no dedicated instruction exists.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | none | not available | No dedicated instruction exists because none is needed: under x86's TSO memory model an ordinary MOV load already has acquire semantics. Compilers emit a plain load for a C++ memory_order_acquire load. |
| ARM | one instruction | LDAR is a first-class acquire load, and LDAXR combines acquire with an exclusive reservation. The matching release store is STLR. | |
| RISC-V | one instruction | Acquire is expressed as an aq bit on A-extension atomics; a plain load needs a following FENCE R,RW instead. | |
| PowerISA | an idiom | No acquire load instruction: the idiom is an ordinary load followed by lwsync (or a control dependency plus isync) to prevent later accesses from moving up. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call