Floating-Point Compare

Compare two floating-point values and make the outcome available to later instructions.

Floating Point

Semantics

Where the answer goes is the interesting part: condition flags, a condition-register field, or an ordinary integer register. NaN handling also differs, since an unordered result is neither less, equal, nor greater.

Architecture Instructions Expressed as How this architecture does it
x86 one instruction The result lands in ZF, PF and CF in EFLAGS, with PF marking the unordered NaN case. UCOMISS signals an exception only for signalling NaNs; COMISS signals for quiet ones too.
ARM one instruction Sets the NZCV condition flags, consumed by a following B.cond, CSEL or CSET. One comparison is live at a time, since there is a single flag set.
RISC-V one instruction There are no condition flags anywhere in the architecture, so each comparison writes 0 or 1 into an integer register. That means three separate instructions instead of one compare plus a condition code, and it is the same design choice that removes the carry flag: no hidden state between instructions.
PowerISA one instruction Writes a four-bit result into one of eight Condition Register fields, named by the instruction. Several comparisons can therefore be in flight in different CR fields at once, which is unusual among these four.

Other operations

Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Memory Barrier / Fence No Operation Population Count Read Cycle Counter Rotate Left Sign Extend Byte Spin-Wait Hint System Call