Load-Linked / Store-Conditional

Reserve a memory location on load, then store only if nothing else wrote it in between.

Atomics

Semantics

A read-modify-write built from two instructions and a reservation, rather than one indivisible operation. The store reports whether it succeeded, and the caller retries. Unlike compare-and-swap it detects any intervening write, not merely a changed value.

Architecture Instructions Expressed as How this architecture does it
x86 none not available x86 has no reservation pair at all. The substitute is compare-and-swap, CMPXCHG under a LOCK prefix, which compares values rather than detecting writes. That difference is the ABA problem: a location changed to another value and back looks untouched to CAS, while a store-conditional fails because the reservation was broken.
ARM one instruction LDXR takes an exclusive monitor reservation and STXR stores only while it still holds, reporting success in a register. LDAXR and STLXR fold acquire and release ordering into the same instructions, so a lock needs no separate barrier.
RISC-V one instruction Provided by the A extension, with .aq and .rl ordering bits on each instruction. The specification bounds what may appear between LR and SC and requires implementations to guarantee that a conforming sequence eventually succeeds, so livelock is an architectural concern rather than an implementation accident.
PowerISA one instruction LWARX sets a reservation and STWCX. stores conditionally, reporting success in CR0 so the retry branch reads a condition register rather than a GPR. LDARX and STDCX. are the 64-bit forms.

Other operations

Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load-Acquire Logical and Arithmetic Shift Memory Barrier / Fence No Operation Population Count Read Cycle Counter Rotate Left Sign Extend Byte Spin-Wait Hint System Call