Speculation Barrier
Stop the processor speculating past this point.
Memory Ordering
Semantics
Distinct from a memory barrier, which orders accesses that do happen. This bounds execution that might not have happened at all, and the reason every architecture now has one is Spectre.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | LFENCE began as a load fence and was retrospectively defined as the speculation barrier: instructions after it do not execute until everything before has retired. Reusing an existing instruction avoided needing new silicon on parts already shipped. | |
| ARM | one instruction | SB was added in ARMv8.5 for exactly this, and bounds speculation without paying for ISB's full context synchronisation. ISB remains the fallback on cores that predate it. | |
| RISC-V | an idiom | The base ISA has no speculation barrier. FENCE orders memory accesses but says nothing about speculation. The Zkt extension takes a different route to the same class of problem, promising data-independent timing for a named subset of instructions rather than offering a barrier. | |
| PowerISA | one instruction | ISYNC after a compare-and-branch bounds speculation, the same instruction already used for context synchronisation. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Spin-Wait Hint Stack Push and Pop System Call