Integer Divide
Divide two integer registers, signed or unsigned.
Arithmetic
Semantics
rd = rs1 / rs2 with an architecture-defined result for division by zero: a trap on x86, a defined value on ARM and RISC-V.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | Divides the implicit RDX:RAX pair and raises #DE on divide-by-zero or overflow, so software must guard the divisor. | |
| ARM | one instruction | Never traps: division by zero returns zero, and there is no remainder instruction, so the remainder is computed with MSUB. | |
| RISC-V | one instruction | M extension. Also never traps: division by zero yields all-ones, and REM provides the remainder. | |
| PowerISA | one instruction | An invalid division leaves the result undefined and, in the OE forms, sets the overflow bit rather than trapping. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call