Multiply High
Get the upper half of a product that is twice the register width.
Arithmetic
Semantics
hi = (a * b) >> N for N-bit operands. Needed for wide arithmetic, and for the multiply-and-shift trick that replaces division by a constant.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | The one-operand forms of MUL and IMUL produce a double-width result across EDX:EAX or RDX:RAX, so the high half arrives with the low one. The cost is that the register pair is implicit rather than chosen. | |
| ARM | one instruction | SMULH and UMULH return only the top 64 bits of a 64x64 product. The low half is a separate MUL, so a full 128-bit product is two instructions, with every operand explicit. | |
| RISC-V | one instruction | From the M extension, and the same shape as ARM's. The specification explicitly recommends emitting MULH and MUL adjacently on the same operands so an implementation can fuse them into a single multiply. | |
| PowerISA | one instruction | MULHD and MULHW give the high half for 64- and 32-bit operands, paired with MULLD and MULLW for the low half. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call