Memory Barrier / Fence

Order memory operations before the barrier against those after it.

Memory Ordering

Semantics

Constrains the visible order of memory accesses across the barrier. How much ordering is needed depends on the architecture's memory model: x86 is TSO and needs a fence mainly for store-load ordering, while ARM, RISC-V, and PowerISA are weakly ordered and need explicit barriers far more often.

Architecture Instructions Expressed as How this architecture does it
x86 one instruction Because x86 is TSO, the only reordering an ordinary program sees is store-to-load, so MFENCE (or a LOCKed instruction) is usually all that is needed. LFENCE also serves as a speculation barrier.
ARM one instruction Weakly ordered, so barriers are needed far more often. DMB orders memory accesses, the stronger DSB waits for completion, and both take shareability/access-type qualifiers such as DMB ISHLD.
RISC-V one instruction One instruction with explicit predecessor and successor sets: FENCE RW,RW orders reads and writes both ways, so the required ordering is spelled out rather than implied.
PowerISA one instruction A graded family: lwsync is the cheap ordering barrier used for acquire/release, sync is the full heavyweight barrier, and eieio orders device-memory accesses.

Other operations

Add With Carry Atomic Compare and Swap Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Floating-Point Square Root Fused Multiply-Add Integer Addition Integer Divide Integer Multiply Load-Acquire No Operation Population Count Rotate Left Sign Extend Byte System Call