Sign Extend Byte
Sign-extend the low byte of a register to the full register width.
Bit Manipulation
Semantics
rd = SignExtend(rs1[7:0]). A base instruction on PowerISA and ARM, an extension (Zbb) on RISC-V, and a load/move form on x86.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | Sign extension happens as part of the move rather than as a standalone operation. | |
| ARM | one instruction | An alias of the bitfield instruction SBFM, like most AArch64 extend and shift mnemonics. | |
| RISC-V | one instruction | Zbb. In the base ISA the same effect requires a shift-left followed by an arithmetic shift-right. | |
| PowerISA | one instruction | Base instruction, with extsh and extsw for the wider forms. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call