Zbb Instructions
17 RISC-V instructions in this extension - click any row for encoding, pseudocode, and full documentation.
| Mnemonic | Syntax | Format | Summary |
|---|---|---|---|
| ANDN | ANDN rd, rs1, rs2 | R-Type | Performs bitwise AND with the bitwise negation of rs2 (rs1 & ~rs2). |
| CLZ | CLZ rd, rs1 | I-Type | Counts the number of 0 bits at the MSB end of the register. |
| CPOP | CPOP rd, rs1 | I-Type | Counts the number of set bits (1s) in the register. |
| CTZ | CTZ rd, rs1 | I-Type | Counts the number of 0 bits at the LSB end of the register. |
| MAX | MAX rd, rs1, rs2 | R-Type | Computes the signed maximum of two registers. |
| MAXU | MAXU rd, rs1, rs2 | R-Type | Computes the maximum of two unsigned integers. |
| MIN | MIN rd, rs1, rs2 | R-Type | Computes the signed minimum of two registers. |
| MINU | MINU rd, rs1, rs2 | R-Type | Computes the minimum of two unsigned integers. |
| ORC.B | ORC.B rd, rs1 | I-Type | Sets each byte of the result to 0xFF if the corresponding byte of the source is non-zero, else 0x00. |
| ORN | ORN rd, rs1, rs2 | R-Type | Performs bitwise OR with the bitwise negation of rs2 (rs1 | ~rs2). |
| REV8 | REV8 rd, rs1 | I-Type | Reverses the order of bytes in a register (Endian swap). |
| ROL | ROL rd, rs1, rs2 | R-Type | Rotates the bits in rs1 left by the amount in rs2. |
| ROR | ROR rd, rs1, rs2 | R-Type | Rotates the bits in rs1 right by the amount in rs2. |
| SEXT.B | SEXT.B rd, rs1 | I-Type | Sign-extends the lowest byte (8 bits) to XLEN bits. |
| SEXT.H | SEXT.H rd, rs1 | I-Type | Sign-extends the lowest halfword (16 bits) to XLEN bits. |
| XNOR | XNOR rd, rs1, rs2 | R-Type | Performs bitwise exclusive-NOR (rs1 ^ ~rs2). |
| ZEXT.H | ZEXT.H rd, rs1 | I-Type | Zero-extends the lowest halfword (16 bits) to XLEN bits. |