Atomic Exchange
Swap a register value with a memory location, indivisibly.
Atomics
Semantics
The simplest useful atomic operation and the basis of a test-and-set lock. Some architectures have a dedicated instruction; others build it from a reservation loop.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | XCHG with a memory operand is atomic whether or not a LOCK prefix is written: the lock is implicit. It is the only x86 read-modify-write instruction that behaves this way, which makes it a common accidental source of full barriers. | |
| ARM | one instruction | SWP and its ordered variants come from FEAT_LSE in ARMv8.1 and do the exchange in one instruction. On cores without LSE, and in code that must run on them, the same job is an LDXR/STXR retry loop. | |
| RISC-V | one instruction | AMOSWAP.W and .D come from the A extension and carry optional .aq and .rl ordering bits, so acquire semantics need no separate fence. | |
| PowerISA | an idiom | There is no dedicated exchange instruction. The idiom is an LWARX/STWCX. loop, the same reservation pair used for compare-and-swap, so exchange and CAS cost the same here while they differ elsewhere. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Memory Barrier / Fence No Operation Population Count Read Cycle Counter Rotate Left Sign Extend Byte Spin-Wait Hint System Call