Conditional Select (Branchless Move)

Choose between two values based on a condition, without branching.

Control Flow

Semantics

rd = cond ? a : b, evaluated without a taken branch, so the result is not exposed to branch misprediction or branch-based timing side channels.

Architecture Instructions Expressed as How this architecture does it
x86 one instruction CMOVcc reads the flags set by a previous compare; there is one mnemonic per condition code.
ARM one instruction The conditional-select family is central to AArch64's branchless style: variants also increment, negate, or invert the second operand (CSINC, CSNEG, CSINV).
RISC-V one instruction The base ISA has no conditional move at all. Zicond adds conditional-ZERO primitives instead, from which a select is built with an OR of two complementary CZERO results.
PowerISA one instruction isel selects between two registers based on any bit of the condition register.

Other operations

Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call