Conditional Select (Branchless Move)
Choose between two values based on a condition, without branching.
Control Flow
Semantics
rd = cond ? a : b, evaluated without a taken branch, so the result is not exposed to branch misprediction or branch-based timing side channels.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | CMOVcc reads the flags set by a previous compare; there is one mnemonic per condition code. | |
| ARM | one instruction | The conditional-select family is central to AArch64's branchless style: variants also increment, negate, or invert the second operand (CSINC, CSNEG, CSINV). | |
| RISC-V | one instruction | The base ISA has no conditional move at all. Zicond adds conditional-ZERO primitives instead, from which a select is built with an OR of two complementary CZERO results. | |
| PowerISA | one instruction | isel selects between two registers based on any bit of the condition register. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) Cache Line Flush Cache Prefetch Hint Compare and Branch Count Leading Zeros Count Trailing Zeros Floating-Point Square Root Fused Multiply-Add Integer Addition Integer Divide Integer Multiply Load-Acquire Memory Barrier / Fence No Operation Population Count Rotate Left Sign Extend Byte System Call