Count Trailing Zeros
Count zero bits below the least significant set bit.
Bit Manipulation
Semantics
rd = ctz(rs1). AArch64 has no direct CTZ: the idiom is RBIT (reverse bits) followed by CLZ.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | Same pairing as the leading-zero case: TZCNT (BMI1) is defined for zero, the older BSF is not. | |
| ARM | an idiom | No direct CTZ. The architectural idiom is RBIT to reverse the bit order followed by CLZ, which is why AArch64 provides a bit-reverse instruction at all. | |
| RISC-V | one instruction | Zbb provides CTZ directly, so unlike AArch64 no bit-reverse step is needed; CTZW covers the 32-bit form on RV64. | |
| PowerISA | one instruction | Added in Power ISA v3.0 alongside the existing leading-zero counts. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call