Count Trailing Zeros
Count zero bits below the least significant set bit.
Bit Manipulation
Semantics
rd = ctz(rs1). AArch64 has no direct CTZ: the idiom is RBIT (reverse bits) followed by CLZ.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | Same pairing as the leading-zero case: TZCNT (BMI1) is defined for zero, the older BSF is not. | |
| ARM | an idiom | No direct CTZ. The architectural idiom is RBIT to reverse the bit order followed by CLZ, which is why AArch64 provides a bit-reverse instruction at all. | |
| RISC-V | one instruction | Zbb provides CTZ directly, so unlike AArch64 no bit-reverse step is needed; CTZW covers the 32-bit form on RV64. | |
| PowerISA | one instruction | Added in Power ISA v3.0 alongside the existing leading-zero counts. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Floating-Point Square Root Fused Multiply-Add Integer Addition Integer Divide Integer Multiply Load-Acquire Memory Barrier / Fence No Operation Population Count Rotate Left Sign Extend Byte System Call