Materialise a Large Constant

Get an arbitrary integer constant into a register.

Data Movement

Semantics

rd = imm, for an immediate too wide to fit in one instruction's encoding. How many instructions this takes is decided by the instruction width, which is why it differs so sharply between a variable-length and a fixed-length architecture.

Architecture Instructions Expressed as How this architecture does it
x86 one instruction MOV r64, imm64 carries a full 64-bit immediate in a single ten-byte instruction. Variable-length encoding means the constant can simply be as wide as it needs to be.
ARM an idiom A 32-bit instruction cannot hold a 64-bit immediate. MOVZ writes one 16-bit field and zeroes the rest, then up to three MOVKs fill the others, so an arbitrary 64-bit constant costs four instructions. MOVN builds values with many high one-bits in fewer.
RISC-V an idiom LUI supplies the upper 20 bits and ADDI the low 12, so a 32-bit constant is two instructions. A full 64-bit constant needs a longer sequence or a load from a literal pool, which is why RISC-V binaries carry more constant pools than x86 ones.
PowerISA an idiom ADDIS (usually written as the LIS alias) sets the high half and ORI the low half: two instructions for 32 bits, more for 64. The split is the same idea as RISC-V's, arrived at independently.

Other operations

Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Memory Barrier / Fence Multiply High No Operation PC-Relative Address Population Count Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call