Population Count
Count the number of set bits in a register.
Bit Manipulation
Semantics
rd = popcount(rs1). Present as a base instruction on PowerISA, an extension on x86 and RISC-V, and only as a SIMD byte-wise operation on AArch64.
| Architecture | Instructions | Expressed as | How this architecture does it |
|---|---|---|---|
| x86 | one instruction | Introduced with SSE4.2 and reported by its own CPUID bit, so portable code still needs a fallback path. | |
| ARM | an idiom | AArch64 has no scalar population count: CNT is a SIMD instruction counting bits per BYTE, so a register-wide count is CNT followed by ADDV to sum the lanes (FEAT_CSSC later adds a scalar CNT). | |
| RISC-V | one instruction | Zbb bit-manipulation extension, which also supplies CPOPW for the 32-bit form on RV64. Base RV64I code without Zbb falls back to the classic SWAR bit-twiddling sequence. | |
| PowerISA | one instruction | Available in the base ISA at three granularities: per doubleword, per word, and per byte. |
Other operations
Add With Carry Atomic Compare and Swap Atomic Exchange Atomic Fetch and Add Breakpoint Trap Byte Swap (Endianness Reversal) CPU Feature Detection Cache Line Flush Cache Prefetch Hint Compare and Branch Conditional Select (Branchless Move) Count Leading Zeros Count Trailing Zeros Enable and Disable Interrupts Floating-Point Compare Floating-Point Square Root Function Call and Return Fused Multiply-Add Indirect Branch Instruction Cache Synchronisation Integer Addition Integer Divide Integer Multiply Integer and Floating-Point Conversion Load and Store Load-Acquire Load-Linked / Store-Conditional Logical and Arithmetic Shift Materialise a Large Constant Memory Barrier / Fence Multiply High No Operation PC-Relative Address Read Cycle Counter Return From Exception Rotate Left Sign Extend Byte Speculation Barrier Spin-Wait Hint Stack Push and Pop System Call