FENCE

Fence

FENCE pred, succ

Orders device I/O and memory accesses.

Encoding

Binary Layout

fm

31:28

pred

27:24

succ

23:20

rs1

19:15

000

14:12

rd

11:7

0001111

6:0

 

Format I-Type

Opcode 0x0000000F

Extension RV32I

Operands

• pred
  Predecessor Set
• succ
  Successor Set

Example

FENCE rw, rw

// Ensures all previous reads/writes complete before subsequent reads/writes.

Related

Across architectures

Memory Barrier / Fence : how x86, ARM, RISC-V, and PowerISA each do this.

More in RV32I

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

FENCE orders device I/O and memory accesses as viewed by other RISC-V harts and external devices. The predecessor and successor sets of operations are specified by the pred and succ fields. FENCE with all fields zero is a full memory fence.

Operation

MemoryBarrier(pred, succ);