VSADDU.VV

Vector Saturating Integer Add Unsigned

VSADDU.VV vd, vs2, vs1, vm

Adds unsigned integers with saturation (clips to max instead of wrapping).

Details

Performs element-wise unsigned saturating add on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.

Pseudocode Operation

foreach(i < vl): vd[i] = saturate_u(vs1[i] + vs2[i]);

Example

VSADDU.VV v1, v4, v2, v0.t

Encoding

Binary Layout
100000
31:26
vm
25
vs2
24:20
vs1
19:15
000
14:12
vd
11:7
1010111
6:0
 
Format OPIVV
Opcode 0x57
Extension V

Operands

  • vd
    Destination vector register
  • vs2
    Source vector register 2
  • vs1
    Source vector register 1