VSRA.VV

Vector Shift Right Arithmetic

VSRA.VV vd, vs2, vs1, vm

Shifts elements of vector vs2 right (arithmetic) by amounts in vs1.

Details

Performs element-wise right arithmetic shift on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.

Pseudocode Operation

foreach(i < vl): vd[i] = vs2[i] >>s (vs1[i] & Mask);

Example

VSRA.VV v1, v4, v2, v0.t

Encoding

Binary Layout
101001
31:26
vm
25
vs2
24:20
vs1
19:15
000
14:12
vd
11:7
1010111
6:0
 
Format OPIVV
Opcode 0x57
Extension V

Operands

  • vd
    Destination vector register
  • vs2
    Source
  • vs1
    Shift Amount