VSSRA.VV

Vector Saturating Shift Right Arithmetic

VSSRA.VV vd, vs2, vs1, vm

Shifts right with sign extension and rounding/saturation logic.

Details

Vector Saturating Shift Right Arithmetic: Shifts right with sign extension and rounding/saturation logic. Operation: foreach(i < vl): vd[i] = saturate(vs2[i] >>s vs1[i]);.

Pseudocode Operation

foreach(i < vl): vd[i] = saturate(vs2[i] >>s vs1[i]);

Example

VSSRA.VV v1, v4, v2, v0.t

Encoding

Binary Layout
101001
31:26
vm
25
vs2
24:20
vs1
19:15
000
14:12
vd
11:7
1010111
6:0
 
Format OPIVV
Opcode 0x57
Extension V

Operands

  • vd
    Destination vector register
  • vs2
    Source
  • vs1
    Source vector register 1