SLLW

Shift Left Logical Word

SLLW rd, rs1, rs2

Performs a 32-bit logical left shift on rs1 by the amount in rs2 (lower 5 bits), sign-extending the result.

Details

SLLW performs a logical left shift of the lower 32 bits of rs1 by the shift amount in the lower 5 bits of rs2, sign-extends the 32-bit result to 64 bits, and writes to rd.

Pseudocode Operation

R[rd] = sext((R[rs1] << (R[rs2] & 0x1F))[31:0]);

Example

SLLW x5, x6, x7

Encoding

Binary Layout
0000000
31:25
rs2
24:20
rs1
19:15
001
14:12
rd
11:7
0111011
6:0
 
Format R-Type
Opcode 0x3B
Extension RV64I

Operands

  • rd
    Destination register (integer)
  • rs1
    Source
  • rs2
    Shift Amount