SLT

Set Less Than

SLT rd, rs1, rs2

Sets rd to 1 if rs1 < rs2 (signed), otherwise 0.

Encoding

Binary Layout

0000000

31:25

rs2

24:20

rs1

19:15

010

14:12

rd

11:7

0110011

6:0

 

Format R-Type

Opcode 0x00002033

Extension RV32I

Operands

• rd
  Destination register (integer)
• rs1
  Source register 1 (integer)
• rs2
  Source register 2 (integer)

Example

SLT x5, x6, x7

// Check if x6 < x7.

Related

More in RV32I

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

SLT performs a signed comparison of rs1 and rs2, writing 1 to rd if rs1 < rs2 (signed), and 0 otherwise.

Operation

R[rd] = (R[rs1] <s R[rs2]) ? 1 : 0;