OR
Logical OR
OR rd, rs1, rs2
Performs a bitwise logical OR operation.
Encoding
Binary Layout
0000000
31:25
rs2
24:20
rs1
19:15
110
14:12
rd
11:7
0110011
6:0
Operands
-
rd
Destination register (integer) -
rs1
Source register 1 (integer) -
rs2
Source register 2 (integer)
Example
OR x10, x11, x12
// Bitwise OR of x11 and x12.
Related
More in RV32I
Reference
View in RISC-V Unprivileged ISA Specification ↗
RISC-V ISA Manual
Description
OR performs a bitwise logical OR of the values in rs1 and rs2, writing the result to rd.
Operation
R[rd] = R[rs1] | R[rs2];