SRA

Shift Right Arithmetic

SRA rd, rs1, rs2

Shifts a register right, preserving the sign bit.

Encoding

Binary Layout

0100000

31:25

rs2

24:20

rs1

19:15

101

14:12

rd

11:7

0110011

6:0

 

Format R-Type

Opcode 0x40005033

Extension RV32I

Operands

• rd
  Destination register (integer)
• rs1
  Source
• rs2
  Shift Amount

Example

SRA x10, x11, x12

// Arithmetic right shift (sign preserved).

Related

More in RV32I

Reference

View in RISC-V Unprivileged ISA Specification ↗ RISC-V ISA Manual

Description

SRA performs an arithmetic right shift of the value in rs1 by the shift amount held in the lower 5 bits of rs2 (or 6 bits in RV64I), writing the result to rd. The original sign bit is copied into the vacated upper bits.

Operation

R[rd] = R[rs1] >>s (R[rs2] & 0x1F);