VFMADD.VV

Vector Float Fused Multiply-Add

VFMADD.VV vd, vs1, vs2, vm

Computes (vs1 * vs2) + vd (overwriting vd) with single rounding.

Details

Performs element-wise FP fused multiply-add on two vector registers, writing results to vd. The number of elements processed is determined by vl, and masking is controlled by vm.

Pseudocode Operation

foreach(i < vl): vd[i] = (vs1[i] * vs2[i]) + vd[i];

Example

VFMADD.VV v1, v2, v4, v0.t

Encoding

Binary Layout
101000
31:26
vm
25
vs2
24:20
vs1
19:15
001
14:12
vd
11:7
1010111
6:0
 
Format OPFVV
Opcode 0x57
Extension V

Operands

  • vd
    Dest/Addend
  • vs1
    Source vector register 1
  • vs2
    Source vector register 2